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rational: tables mirror-exact from the designer; the stage.h snap removed - #67

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claude/sample-rate-expansion-strategies-ezqzu6
Oct 8, 2026
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tap merged 1 commit into
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claude/sample-rate-expansion-strategies-ezqzu6

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@tap tap commented Oct 8, 2026

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What this changes

Why

#65 found the 2/3 super_economy Q15 table differing between the host and the Cortex-M legs and worked around it with a snap, leaving the cause as a finding. The cause is in the designer, not the quantizer: nyquist.h summed branch j and its mirror branch in opposite orders, so their gains could differ by an ulp (equal under glibc, unequal under newlib for that design), and a mirrored pair that lands in one quantized row tied only by luck. DspTap#56 fixes it at the root; this PR takes the pin and drops the mitigation.

Verification

  • Every Q15 pin holds: the snap had already made those ties exact.
  • Two Q31 pins move on the host, each by one LSB moved between the members of a mirror pair with the row sum unchanged (↓6 balanced: branch 0 tap 8 → branch 4 tap 19; 3/4 economy: row 1 tap 11 → tap 17), verified by dumping both tables against the old and new DspTap. These are the two designs where glibc's mirror gains had differed.
  • Host: 286/286 on clang 18; the rational label 113/113 on gcc; clang-tidy clean.
  • Cortex-M33 and M55 under QEMU: the rational battery 7/7 on each, the tables identical to the host's.
  • No ratchet workload changes code on the hot path; nothing in bench/ moves.

Notes for the reviewer

🤖 Generated with Claude Code

https://claude.ai/code/session_015VR1VC4SDGxHZQQsQvPBaA


Generated by Claude Code

…oved

DspTap pinned at tap/DspTap#56: design_nyquist copies its second half
from the first after the per-branch normalization, whose mirror
branches were summed in opposite orders and could carry gains an ulp
apart (equal under glibc, unequal under newlib for the third-band
m = 8 design). That was the cause of the 2/3 super_economy Q15 table
differing between the host and the Cortex-M legs in #65; the 2^-34
snap that PR added to stage.h is removed, since the ties it made exact
are exact by construction now.

Every Q15 pin holds. Two Q31 pins move on the host, ↓6 balanced and
3/4 economy: one LSB moves between the members of a mirror pair
(branch 0 tap 8 to branch 4 tap 19; row 1 tap 11 to tap 17), the row
sums unchanged, the two designs where glibc's mirror gains differed.
The tables are the same on the host, the M33 and the M55.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_015VR1VC4SDGxHZQQsQvPBaA
@tap
tap merged commit d4fff5c into main Oct 8, 2026
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@tap
tap deleted the claude/sample-rate-expansion-strategies-ezqzu6 branch October 8, 2026 12:15
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